Verilog HDL

The process of designing digital logic system by verilog HDL is presented , compared with the traditional digital logic system design method .

通过与传统的数字逻辑系统的设计方法进行比较，展现了硬件描述语言Verilog-HDL设计数字逻辑电路的优越性。

A Programmable UART Based on Verilog HDL

基于Verilog硬件描述语言的可编程异步收发器

High Level Design Environment for Digital Integrated Circuit Based on Verilog HDL

基于VerilogHDL的数字集成电路高层设计环境

Analysis of several problems in digital circuit design by verilog HDL

用Veriloghdl设计数字电路过程中的两个问题

Design and Test of CAN Bus Controller Based on Verilog HDL

基于Veriloghdl语言的CAN总线控制器设计及测试

A Verilog HDL - based Pipelining Design Method and its Application

基于Veriloghdl的流水线的设计方法及应用

How to Design a Digital System Using Verilog HDL

如何用Veriloghdl来设计数字系统

Implementation of LED Display Scanning Controller Model Based on Verilog HDL

基于Veriloghdl的LED显示屏扫描控制模块的实现

Rules of CPLD / FPGA System Design Based on Verilog HDL

Veriloghdl语言在FPGA/CPLD系统设计中的几个原则

Two Special Data Types in Verilog HDL and Evaluation of the Variables

Veriloghdl语言中的特殊数据类型及其赋值

The Design Example of Verilog HDL and Its Simulation & Synthesis

Veriloghdl设计实例及其仿真与综合

Implementation of PCI bus object interface status machine using Verilog HDL

PCI总线目标接口状态机的Veriloghdl实现

The Frequency Measuring and Its Fulfilling Method Based on Verilog HDL

频率测量及其Veriloghdl的实现方法

The Basic Methods of FPGA design using Verilog HDL

用Veriloghdl进行FPGA设计的一些基本方法

The Verilog HDL has been used in the paper to describe whole algorithm .

在设计中本文使用了Verilog语言对整个个算法进行了描述。

FPGA realization of SPWM entire digital algorithm based on Verilog HDL

基于Veriloghdl的SPWM全数字算法的FPGA实现

Design of digital circuit based on Verilog HDL

Veriloghdl数字电路的设计

In this paper , Verilog HDL & a hardware description language is introduced .

介绍硬件描述语言Verilog-HDL。

Designing of Traffic Lights with Left Turn Controllers Based on Verilog HDL

基于Veriloghdl语言的带左转复杂交通灯设计

Design of Multifunctional Digital Clock Based on Verilog HDL

基于Veriloghdl设计的多功能数字钟

Research fingerprint recognition algorithm IP core in Verilog HDL ( hardware description language ) .

研究基于Veriloghdl（硬件描述语言）的指纹识别算法IP核。

Verilog HDL : A Descriptive Language for Hardware in EDA Technology

EDA技术中的硬件描述语言&Veriloghdl

Design of encoder for MVB network based on verilog HDL

基于Veriloghdl的多功能车辆总线编码器设计

USB 2.0 Device Controller IP Core For Verilog HDL Designs

USB2.0设备控制器IP核的Veriloghdl设计

Variable step optimization method is realized by Verilog HDL , and conducted a functional simulation .

采用Veriloghdl实现变步长寻优法，并对此进行功能仿真。

The Design of a Circular Adder Based on Verilog HDL

基于Verilog语言的循环式加法器的设计

The Verilog HDL source code is developed , and the functional simulation is completed .

利用Veriloghdl硬件描述语言开发了RTL级代码，并进行了功能仿真。

At the same time verilog HDL simulation results of the main modules are presented in this thesis .

同时给出了主要模块的Veriloghdl的仿真结果。

Design and simulation of digital cross-connect matrix with verilog HDL

基于Verilog语言的数字交叉连接矩阵设计

The Verilog HDL which is understood easily is adopted for the paper .

系统采用一种软件硬化的设计思路，应用了Veriloghdl硬件语言，该语言较容易理解。